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<table class="head">
  <tr>
    <td class="head-ltitle">GBZ80(7)</td>
    <td class="head-vol">Miscellaneous Information Manual</td>
    <td class="head-rtitle">GBZ80(7)</td>
  </tr>
</table>
<div class="manual-text">
<section class="Sh">
<h1 class="Sh" id="NAME"><a class="permalink" href="#NAME">NAME</a></h1>
<code class="Nm">gbz80</code> &#x2014;
<div class="Nd">CPU opcode reference</div>
</section>
<section class="Sh">
<h1 class="Sh" id="DESCRIPTION"><a class="permalink" href="#DESCRIPTION">DESCRIPTION</a></h1>
This is the list of opcodes supported by <a class="Xr">rgbasm(1)</a>, including
  a short description, the number of bytes needed to encode them and the number
  of CPU cycles at 1MHz (or 2MHz in GBC dual speed mode) needed to complete
  them.
<p class="Pp">Note: All arithmetic/logic operations that use register
    <b class="Sy">A</b> as destination can omit the destination as it is assumed
    it's register <b class="Sy">A</b>. The following two lines have the same
    effect:</p>
<div class="Bd Pp Bd-indent">
<pre>
OR A,B
OR B
</pre>
</div>
</section>
<section class="Sh">
<h1 class="Sh" id="LEGEND"><a class="permalink" href="#LEGEND">LEGEND</a></h1>
List of abbreviations used in this document.
<dl class="Bl-tag">
  <dt><var class="Ar">r8</var></dt>
  <dd>Any of the 8-bit registers (<b class="Sy">A</b>, <b class="Sy">B</b>,
      <b class="Sy">C</b>, <b class="Sy">D</b>, <b class="Sy">E</b>,
      <b class="Sy">H</b>, <b class="Sy">L</b>).</dd>
  <dt><var class="Ar">r16</var></dt>
  <dd>Any of the general-purpose 16-bit registers (<b class="Sy">BC</b>,
      <b class="Sy">DE</b>, <b class="Sy">HL</b>).</dd>
  <dt><var class="Ar">n8</var></dt>
  <dd>8-bit integer constant.</dd>
  <dt><var class="Ar">n16</var></dt>
  <dd>16-bit integer constant.</dd>
  <dt><var class="Ar">e8</var></dt>
  <dd>8-bit offset (<code class="Fl">-</code><b class="Sy">128</b> to
      <b class="Sy">127</b>).</dd>
  <dt><var class="Ar">u3</var></dt>
  <dd>3-bit unsigned integer constant (<b class="Sy">0</b> to
      <b class="Sy">7</b>).</dd>
  <dt><var class="Ar">cc</var></dt>
  <dd>Condition codes:
    <dl class="Bl-tag Bl-compact">
      <dt><b class="Sy">Z</b>:</dt>
      <dd>Execute if Z is set.</dd>
      <dt><b class="Sy">NZ</b>:</dt>
      <dd>Execute if Z is not set.</dd>
      <dt><b class="Sy">C</b>:</dt>
      <dd>Execute if C is set.</dd>
      <dt><b class="Sy">NC</b>:</dt>
      <dd>Execute if C is not set.</dd>
    </dl>
  </dd>
  <dt><var class="Ar">vec</var></dt>
  <dd>One of the <var class="Ar">RST</var> vectors (<b class="Sy">0x00</b>,
      <b class="Sy">0x08</b>, <b class="Sy">0x10</b>, <b class="Sy">0x18</b>,
      <b class="Sy">0x20</b>, <b class="Sy">0x28</b>, <b class="Sy">0x30</b> and
      <b class="Sy">0x38</b>).</dd>
</dl>
</section>
<section class="Sh">
<h1 class="Sh" id="INSTRUCTION_OVERVIEW"><a class="permalink" href="#INSTRUCTION_OVERVIEW">INSTRUCTION
  OVERVIEW</a></h1>
<section class="Ss">
<h2 class="Ss" id="8-bit_Arithmetic_and_Logic_Instructions"><a class="permalink" href="#8-bit_Arithmetic_and_Logic_Instructions">8-bit
  Arithmetic and Logic Instructions</a></h2>
<dl class="Bl-inset Bl-compact">
  <dt><a class="Sx" href="#ADC_A,r8">ADC A,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#ADC_A,_HL_">ADC A,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#ADC_A,n8">ADC A,n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#ADD_A,r8">ADD A,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#ADD_A,_HL_">ADD A,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#ADD_A,n8">ADD A,n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#AND_A,r8">AND A,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#AND_A,_HL_">AND A,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#AND_A,n8">AND A,n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#CP_A,r8">CP A,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#CP_A,_HL_">CP A,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#CP_A,n8">CP A,n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#DEC_r8">DEC r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#DEC__HL_">DEC [HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#INC_r8">INC r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#INC__HL_">INC [HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#OR_A,r8">OR A,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#OR_A,_HL_">OR A,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#OR_A,n8">OR A,n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SBC_A,r8">SBC A,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SBC_A,_HL_">SBC A,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SBC_A,n8">SBC A,n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SUB_A,r8">SUB A,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SUB_A,_HL_">SUB A,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SUB_A,n8">SUB A,n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#XOR_A,r8">XOR A,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#XOR_A,_HL_">XOR A,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#XOR_A,n8">XOR A,n8</a></dt>
  <dd></dd>
</dl>
</section>
<section class="Ss">
<h2 class="Ss" id="16-bit_Arithmetic_Instructions"><a class="permalink" href="#16-bit_Arithmetic_Instructions">16-bit
  Arithmetic Instructions</a></h2>
<dl class="Bl-inset Bl-compact">
  <dt><a class="Sx" href="#ADD_HL,r16">ADD HL,r16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#DEC_r16">DEC r16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#INC_r16">INC r16</a></dt>
  <dd></dd>
</dl>
</section>
<section class="Ss">
<h2 class="Ss" id="Bit_Operations_Instructions"><a class="permalink" href="#Bit_Operations_Instructions">Bit
  Operations Instructions</a></h2>
<dl class="Bl-inset Bl-compact">
  <dt><a class="Sx" href="#BIT_u3,r8">BIT u3,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#BIT_u3,_HL_">BIT u3,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RES_u3,r8">RES u3,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RES_u3,_HL_">RES u3,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SET_u3,r8">SET u3,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SET_u3,_HL_">SET u3,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SWAP_r8">SWAP r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SWAP__HL_">SWAP [HL]</a></dt>
  <dd></dd>
</dl>
</section>
<section class="Ss">
<h2 class="Ss" id="Bit_Shift_Instructions"><a class="permalink" href="#Bit_Shift_Instructions">Bit
  Shift Instructions</a></h2>
<dl class="Bl-inset Bl-compact">
  <dt><a class="Sx" href="#RL_r8">RL r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RL__HL_">RL [HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RLA">RLA</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RLC_r8">RLC r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RLC__HL_">RLC [HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RLCA">RLCA</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RR_r8">RR r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RR__HL_">RR [HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RRA">RRA</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RRC_r8">RRC r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RRC__HL_">RRC [HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RRCA">RRCA</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SLA_r8">SLA r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SLA__HL_">SLA [HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SRA_r8">SRA r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SRA__HL_">SRA [HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SRL_r8">SRL r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SRL__HL_">SRL [HL]</a></dt>
  <dd></dd>
</dl>
</section>
<section class="Ss">
<h2 class="Ss" id="Load_Instructions"><a class="permalink" href="#Load_Instructions">Load
  Instructions</a></h2>
<dl class="Bl-inset Bl-compact">
  <dt><a class="Sx" href="#LD_r8,r8">LD r8,r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_r8,n8">LD r8,n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_r16,n16">LD r16,n16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__HL_,r8">LD [HL],r8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__HL_,n8">LD [HL],n8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_r8,_HL_">LD r8,[HL]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__r16_,A">LD [r16],A</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__n16_,A">LD [n16],A</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__$FF00+n8_,A">LD [$FF00+n8],A</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__$FF00+C_,A">LD [$FF00+C],A</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_A,_r16_">LD A,[r16]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_A,_n16_">LD A,[n16]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_A,_$FF00+n8_">LD A,[$FF00+n8]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_A,_$FF00+C_">LD A,[$FF00+C]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__HL+_,A">LD [HL+],A</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__HL-_,A">LD [HL-],A</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_A,_HL+_">LD A,[HL+]</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_A,_HL-_">LD A,[HL-]</a></dt>
  <dd></dd>
</dl>
</section>
<section class="Ss">
<h2 class="Ss" id="Jumps_and_Subroutines"><a class="permalink" href="#Jumps_and_Subroutines">Jumps
  and Subroutines</a></h2>
<dl class="Bl-inset Bl-compact">
  <dt><a class="Sx" href="#CALL_n16">CALL n16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#CALL_cc,n16">CALL cc,n16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#JP_HL">JP HL</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#JP_n16">JP n16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#JP_cc,n16">JP cc,n16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#JR_e8">JR e8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#JR_cc,e8">JR cc,e8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RET_cc">RET cc</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RET">RET</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RETI">RETI</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#RST_vec">RST vec</a></dt>
  <dd></dd>
</dl>
</section>
<section class="Ss">
<h2 class="Ss" id="Stack_Operations_Instructions"><a class="permalink" href="#Stack_Operations_Instructions">Stack
  Operations Instructions</a></h2>
<dl class="Bl-inset Bl-compact">
  <dt><a class="Sx" href="#ADD_HL,SP">ADD HL,SP</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#ADD_SP,e8">ADD SP,e8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#DEC_SP">DEC SP</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#INC_SP">INC SP</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_SP,n16">LD SP,n16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD__n16_,SP">LD [n16],SP</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_HL,SP+e8">LD HL,SP+e8</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#LD_SP,HL">LD SP,HL</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#POP_AF">POP AF</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#POP_r16">POP r16</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#PUSH_AF">PUSH AF</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#PUSH_r16">PUSH r16</a></dt>
  <dd></dd>
</dl>
</section>
<section class="Ss">
<h2 class="Ss" id="Miscellaneous_Instructions"><a class="permalink" href="#Miscellaneous_Instructions">Miscellaneous
  Instructions</a></h2>
<dl class="Bl-inset Bl-compact">
  <dt><a class="Sx" href="#CCF">CCF</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#CPL">CPL</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#DAA">DAA</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#DI">DI</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#EI">EI</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#HALT">HALT</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#NOP">NOP</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#SCF">SCF</a></dt>
  <dd></dd>
  <dt><a class="Sx" href="#STOP">STOP</a></dt>
  <dd></dd>
</dl>
</section>
</section>
<section class="Sh">
<h1 class="Sh" id="INSTRUCTION_REFERENCE"><a class="permalink" href="#INSTRUCTION_REFERENCE">INSTRUCTION
  REFERENCE</a></h1>
<section class="Ss">
<h2 class="Ss" id="ADC_A,r8"><a class="permalink" href="#ADC_A,r8">ADC
  A,r8</a></h2>
Add the value in <var class="Ar">r8</var> plus the carry flag to
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: Set if overflow from bit 3.</li>
  <li><b class="Sy">C</b>: Set if overflow from bit 7.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="ADC_A,_HL_"><a class="permalink" href="#ADC_A,_HL_">ADC
  A,[HL]</a></h2>
Add the value pointed by <b class="Sy">HL</b> plus the carry flag to
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#ADC_A,r8">ADC A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="ADC_A,n8"><a class="permalink" href="#ADC_A,n8">ADC
  A,n8</a></h2>
Add the value <var class="Ar">n8</var> plus the carry flag to
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#ADC_A,r8">ADC A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="ADD_A,r8"><a class="permalink" href="#ADD_A,r8">ADD
  A,r8</a></h2>
Add the value in <var class="Ar">r8</var> to <b class="Sy">A</b>.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: Set if overflow from bit 3.</li>
  <li><b class="Sy">C</b>: Set if overflow from bit 7.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="ADD_A,_HL_"><a class="permalink" href="#ADD_A,_HL_">ADD
  A,[HL]</a></h2>
Add the value pointed by <b class="Sy">HL</b> to <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#ADD_A,r8">ADD A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="ADD_A,n8"><a class="permalink" href="#ADD_A,n8">ADD
  A,n8</a></h2>
Add the value <var class="Ar">n8</var> to <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#ADD_A,r8">ADD A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="ADD_HL,r16"><a class="permalink" href="#ADD_HL,r16">ADD
  HL,r16</a></h2>
Add the value in <var class="Ar">r16</var> to <b class="Sy">HL</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: Set if overflow from bit 11.</li>
  <li><b class="Sy">C</b>: Set if overflow from bit 15.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="ADD_HL,SP"><a class="permalink" href="#ADD_HL,SP">ADD
  HL,SP</a></h2>
Add the value in <b class="Sy">SP</b> to <b class="Sy">HL</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#ADD_HL,r16">ADD HL,r16</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="ADD_SP,e8"><a class="permalink" href="#ADD_SP,e8">ADD
  SP,e8</a></h2>
Add the signed value <var class="Ar">e8</var> to <b class="Sy">SP</b>.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: 0</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: Set if overflow from bit 3.</li>
  <li><b class="Sy">C</b>: Set if overflow from bit 7.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="AND_A,r8"><a class="permalink" href="#AND_A,r8">AND
  A,r8</a></h2>
Bitwise AND between the value in <var class="Ar">r8</var> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 1</li>
  <li><b class="Sy">C</b>: 0</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="AND_A,_HL_"><a class="permalink" href="#AND_A,_HL_">AND
  A,[HL]</a></h2>
Bitwise AND between the value pointed by <b class="Sy">HL</b> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#AND_A,r8">AND A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="AND_A,n8"><a class="permalink" href="#AND_A,n8">AND
  A,n8</a></h2>
Bitwise AND between the value in <var class="Ar">n8</var> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#AND_A,r8">AND A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="BIT_u3,r8"><a class="permalink" href="#BIT_u3,r8">BIT
  u3,r8</a></h2>
Test bit <var class="Ar">u3</var> in register <var class="Ar">r8</var>, set the
  zero flag if bit not set.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if the selected bit is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 1</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="BIT_u3,_HL_"><a class="permalink" href="#BIT_u3,_HL_">BIT
  u3,[HL]</a></h2>
Test bit <var class="Ar">u3</var> in the byte pointed by <b class="Sy">HL</b>,
  set the zero flag if bit not set.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#BIT_u3,r8">BIT u3,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="CALL_n16"><a class="permalink" href="#CALL_n16">CALL
  n16</a></h2>
Call address <var class="Ar">n16</var>.
<p class="Pp">Cycles: 6</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="CALL_cc,n16"><a class="permalink" href="#CALL_cc,n16">CALL
  cc,n16</a></h2>
Call address <var class="Ar">n16</var> if condition <var class="Ar">cc</var> is
  met.
<p class="Pp">Cycles: 6/3</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="CCF"><a class="permalink" href="#CCF">CCF</a></h2>
Complement Carry Flag.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Complemented.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="CP_A,r8"><a class="permalink" href="#CP_A,r8">CP
  A,r8</a></h2>
Subtract the value in <var class="Ar">r8</var> from <b class="Sy">A</b> and set
  flags accordingly, but don't store the result.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 1</li>
  <li><b class="Sy">H</b>: Set if no borrow from bit 4.</li>
  <li><b class="Sy">C</b>: Set if no borrow (set if <var class="Ar">r8</var>
      &gt; <b class="Sy">A</b>).</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="CP_A,_HL_"><a class="permalink" href="#CP_A,_HL_">CP
  A,[HL]</a></h2>
Subtract the value pointed by <b class="Sy">HL</b> from <b class="Sy">A</b> and
  set flags accordingly, but don't store the result.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#CP_A,r8">CP A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="CP_A,n8"><a class="permalink" href="#CP_A,n8">CP
  A,n8</a></h2>
Subtract the value <var class="Ar">n8</var> from <b class="Sy">A</b> and set
  flags accordingly, but don't store the result.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#CP_A,r8">CP A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="CPL"><a class="permalink" href="#CPL">CPL</a></h2>
Complement accumulator (<b class="Sy">A</b> = <b class="Sy">~A</b>).
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">N</b>: 1</li>
  <li><b class="Sy">H</b>: 1</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="DAA"><a class="permalink" href="#DAA">DAA</a></h2>
Decimal adjust register A to get a correct BCD representation after an
  arithmetic instruction.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set or reset depending on the operation.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="DEC_r8"><a class="permalink" href="#DEC_r8">DEC r8</a></h2>
Decrement value in register <var class="Ar">r8</var> by 1.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 1</li>
  <li><b class="Sy">H</b>: Set if no borrow from bit 4.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="DEC__HL_"><a class="permalink" href="#DEC__HL_">DEC
  [HL]</a></h2>
Decrement the value pointed by <b class="Sy">HL</b> by 1.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#DEC_r8">DEC r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="DEC_r16"><a class="permalink" href="#DEC_r16">DEC
  r16</a></h2>
Decrement value in register <var class="Ar">r16</var> by 1.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="DEC_SP"><a class="permalink" href="#DEC_SP">DEC SP</a></h2>
Decrement value in register <b class="Sy">SP</b> by 1.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="DI"><a class="permalink" href="#DI">DI</a></h2>
Disable Interrupts.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="EI"><a class="permalink" href="#EI">EI</a></h2>
Enable Interrupts.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="HALT"><a class="permalink" href="#HALT">HALT</a></h2>
Enter CPU low power mode.
<p class="Pp">Cycles: -</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="INC_r8"><a class="permalink" href="#INC_r8">INC r8</a></h2>
Increment value in register <var class="Ar">r8</var> by 1.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: Set if overflow from bit 3.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="INC__HL_"><a class="permalink" href="#INC__HL_">INC
  [HL]</a></h2>
Increment the value pointed by <b class="Sy">HL</b> by 1.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#INC_r8">INC r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="INC_r16"><a class="permalink" href="#INC_r16">INC
  r16</a></h2>
Increment value in register <var class="Ar">r16</var> by 1.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="INC_SP"><a class="permalink" href="#INC_SP">INC SP</a></h2>
Increment value in register <b class="Sy">SP</b> by 1.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="JP_n16"><a class="permalink" href="#JP_n16">JP n16</a></h2>
Absolute jump to address <var class="Ar">n16</var>.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="JP_cc,n16"><a class="permalink" href="#JP_cc,n16">JP
  cc,n16</a></h2>
Absolute jump to address <var class="Ar">n16</var> if condition
  <var class="Ar">cc</var> is met.
<p class="Pp">Cycles: 4/3</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="JP_HL"><a class="permalink" href="#JP_HL">JP HL</a></h2>
Jump to address in <b class="Sy">HL</b>, that is, load <b class="Sy">PC</b> with
  value in register <b class="Sy">HL</b>.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="JR_e8"><a class="permalink" href="#JR_e8">JR e8</a></h2>
Relative jump by adding <var class="Ar">e8</var> to the current address.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="JR_cc,e8"><a class="permalink" href="#JR_cc,e8">JR
  cc,e8</a></h2>
Relative jump by adding <var class="Ar">e8</var> to the current address if
  condition <var class="Ar">cc</var> is met.
<p class="Pp">Cycles: 3/2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_r8,r8"><a class="permalink" href="#LD_r8,r8">LD
  r8,r8</a></h2>
Store value in register on the right into register on the left.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_r8,n8"><a class="permalink" href="#LD_r8,n8">LD
  r8,n8</a></h2>
Load value <var class="Ar">n8</var> into register <var class="Ar">r8</var>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_r16,n16"><a class="permalink" href="#LD_r16,n16">LD
  r16,n16</a></h2>
Load value <var class="Ar">n16</var> into register <var class="Ar">r16</var>.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__HL_,r8"><a class="permalink" href="#LD__HL_,r8">LD
  [HL],r8</a></h2>
Store value in register <var class="Ar">r8</var> into byte pointed by register
  <b class="Sy">HL</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__HL_,n8"><a class="permalink" href="#LD__HL_,n8">LD
  [HL],n8</a></h2>
Store value <var class="Ar">n8</var> into byte pointed by register
  <b class="Sy">HL</b>.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_r8,_HL_"><a class="permalink" href="#LD_r8,_HL_">LD
  r8,[HL]</a></h2>
Load value into register <var class="Ar">r8</var> from byte pointed by register
  <b class="Sy">HL</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__r16_,A"><a class="permalink" href="#LD__r16_,A">LD
  [r16],A</a></h2>
Store value in register <b class="Sy">A</b> into address pointed by register
  <var class="Ar">r16</var>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__n16_,A"><a class="permalink" href="#LD__n16_,A">LD
  [n16],A</a></h2>
Store value in register <b class="Sy">A</b> into address
  <var class="Ar">n16</var>.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__$FF00+n8_,A"><a class="permalink" href="#LD__$FF00+n8_,A">LD
  [$FF00+n8],A</a></h2>
Store value in register <b class="Sy">A</b> into high RAM or I/O registers.
<p class="Pp">The following synonym forces this encoding: <b class="Sy">LDH
    [$FF00+n8],A</b></p>
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__$FF00+C_,A"><a class="permalink" href="#LD__$FF00+C_,A">LD
  [$FF00+C],A</a></h2>
Store value in register <b class="Sy">A</b> into high RAM or I/O registers.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_A,_r16_"><a class="permalink" href="#LD_A,_r16_">LD
  A,[r16]</a></h2>
Load value in register <b class="Sy">A</b> from address pointed by register
  <var class="Ar">r16</var>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_A,_n16_"><a class="permalink" href="#LD_A,_n16_">LD
  A,[n16]</a></h2>
Load value in register <b class="Sy">A</b> from address
  <var class="Ar">n16</var>.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_A,_$FF00+n8_"><a class="permalink" href="#LD_A,_$FF00+n8_">LD
  A,[$FF00+n8]</a></h2>
Load value in register <b class="Sy">A</b> from high RAM or I/O registers.
<p class="Pp">The following synonym forces this encoding: <b class="Sy">LDH
    A,[$FF00+n8]</b></p>
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_A,_$FF00+C_"><a class="permalink" href="#LD_A,_$FF00+C_">LD
  A,[$FF00+C]</a></h2>
Load value in register <b class="Sy">A</b> from high RAM or I/O registers.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__HL+_,A"><a class="permalink" href="#LD__HL+_,A">LD
  [HL+],A</a></h2>
Store value in register <b class="Sy">A</b> into byte pointed by
  <b class="Sy">HL</b> and post-increment <b class="Sy">HL</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__HL-_,A"><a class="permalink" href="#LD__HL-_,A">LD
  [HL-],A</a></h2>
Store value in register <b class="Sy">A</b> into byte pointed by
  <b class="Sy">HL</b> and post-decrement <b class="Sy">HL</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_A,_HL+_"><a class="permalink" href="#LD_A,_HL+_">LD
  A,[HL+]</a></h2>
Load value into register <b class="Sy">A</b> from byte pointed by
  <b class="Sy">HL</b> and post-increment <b class="Sy">HL</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_A,_HL-_"><a class="permalink" href="#LD_A,_HL-_">LD
  A,[HL-]</a></h2>
Load value into register <b class="Sy">A</b> from byte pointed by
  <b class="Sy">HL</b> and post-decrement <b class="Sy">HL</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_SP,n16"><a class="permalink" href="#LD_SP,n16">LD
  SP,n16</a></h2>
Load value <var class="Ar">n16</var> into register <b class="Sy">SP</b>.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD__n16_,SP"><a class="permalink" href="#LD__n16_,SP">LD
  [n16],SP</a></h2>
Store <b class="Sy">SP</b> into addresses <var class="Ar">n16</var> (LSB) and
  <var class="Ar">n16</var> + 1 (MSB).
<p class="Pp">Cycles: 5</p>
<p class="Pp">Bytes: 3</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_HL,SP+e8"><a class="permalink" href="#LD_HL,SP+e8">LD
  HL,SP+e8</a></h2>
Add the signed value <var class="Ar">e8</var> to <b class="Sy">SP</b> and store
  the result in <b class="Sy">HL.</b>
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: 0</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: Set if overflow from bit 3.</li>
  <li><b class="Sy">C</b>: Set if overflow from bit 7.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="LD_SP,HL"><a class="permalink" href="#LD_SP,HL">LD
  SP,HL</a></h2>
Load register <b class="Sy">HL</b> into register <b class="Sy">SP</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="NOP"><a class="permalink" href="#NOP">NOP</a></h2>
No operation.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="OR_A,r8"><a class="permalink" href="#OR_A,r8">OR
  A,r8</a></h2>
Bitwise OR between the value in <var class="Ar">r8</var> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: 0</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="OR_A,_HL_"><a class="permalink" href="#OR_A,_HL_">OR
  A,[HL]</a></h2>
Bitwise OR between the value pointed by <b class="Sy">HL</b> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#OR_A,r8">OR A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="OR_A,n8"><a class="permalink" href="#OR_A,n8">OR
  A,n8</a></h2>
Bitwise OR between the value in <var class="Ar">n8</var> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#OR_A,r8">OR A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="POP_AF"><a class="permalink" href="#POP_AF">POP AF</a></h2>
Pop register <b class="Sy">AF</b> from the stack.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set from bit 7 of the popped low byte.</li>
  <li><b class="Sy">N</b>: Set from bit 6 of the popped low byte.</li>
  <li><b class="Sy">H</b>: Set from bit 5 of the popped low byte.</li>
  <li><b class="Sy">C</b>: Set from bit 4 of the popped low byte.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="POP_r16"><a class="permalink" href="#POP_r16">POP
  r16</a></h2>
Pop register <var class="Ar">r16</var> from the stack.
<p class="Pp">Cycles: 3</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="PUSH_AF"><a class="permalink" href="#PUSH_AF">PUSH
  AF</a></h2>
Push register <b class="Sy">AF</b> into the stack. The low byte's bit 7
  corresponds to the <b class="Sy">Z</b> flag, its bit 6 to the
  <b class="Sy">N</b> flag, bit 5 to the <b class="Sy">H</b> flag, and bit 4 to
  the <b class="Sy">C</b> flag. Bits 3 to 0 are reset.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="PUSH_r16"><a class="permalink" href="#PUSH_r16">PUSH
  r16</a></h2>
Push register <var class="Ar">r16</var> into the stack.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="RES_u3,r8"><a class="permalink" href="#RES_u3,r8">RES
  u3,r8</a></h2>
Set bit <var class="Ar">u3</var> in register <var class="Ar">r8</var> to 0.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="RES_u3,_HL_"><a class="permalink" href="#RES_u3,_HL_">RES
  u3,[HL]</a></h2>
Set bit <var class="Ar">u3</var> in the byte pointed by <b class="Sy">HL</b> to
  0.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="RET"><a class="permalink" href="#RET">RET</a></h2>
Return from subroutine.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="RET_cc"><a class="permalink" href="#RET_cc">RET cc</a></h2>
Return from subroutine if condition <var class="Ar">cc</var> is met.
<p class="Pp">Cycles: 5/2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="RETI"><a class="permalink" href="#RETI">RETI</a></h2>
Return from subroutine and enable interrupts.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="RL_r8"><a class="permalink" href="#RL_r8">RL r8</a></h2>
Rotate register <var class="Ar">r8</var> left through carry.
<p class="Pp"></p>
<div class="Bd Bd-indent">C &lt;- [7 &lt;- 0] &lt;- C</div>
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="RL__HL_"><a class="permalink" href="#RL__HL_">RL
  [HL]</a></h2>
Rotate value pointed by <b class="Sy">HL</b> left through carry.
<p class="Pp"></p>
<div class="Bd Bd-indent">C &lt;- [7 &lt;- 0] &lt;- C</div>
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#RL_r8">RL r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="RLA"><a class="permalink" href="#RLA">RLA</a></h2>
Rotate register <b class="Sy">A</b> left through carry.
<p class="Pp"></p>
<div class="Bd Bd-indent">C &lt;- [7 &lt;- 0] &lt;- C</div>
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: 0</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="RLC_r8"><a class="permalink" href="#RLC_r8">RLC r8</a></h2>
Rotate register <var class="Ar">r8</var> left.
<p class="Pp"></p>
<div class="Bd Bd-indent">C &lt;- [7 &lt;- 0] &lt;- [7]</div>
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="RLC__HL_"><a class="permalink" href="#RLC__HL_">RLC
  [HL]</a></h2>
Rotate value pointed by <b class="Sy">HL</b> left.
<p class="Pp"></p>
<div class="Bd Bd-indent">C &lt;- [7 &lt;- 0] &lt;- [7]</div>
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#RLC_r8">RLC r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="RLCA"><a class="permalink" href="#RLCA">RLCA</a></h2>
Rotate register <b class="Sy">A</b> left.
<p class="Pp"></p>
<div class="Bd Bd-indent">C &lt;- [7 &lt;- 0] &lt;- [7]</div>
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: 0</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="RR_r8"><a class="permalink" href="#RR_r8">RR r8</a></h2>
Rotate register <var class="Ar">r8</var> right through carry.
<p class="Pp"></p>
<div class="Bd Bd-indent">C -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="RR__HL_"><a class="permalink" href="#RR__HL_">RR
  [HL]</a></h2>
Rotate value pointed by <b class="Sy">HL</b> right through carry.
<p class="Pp"></p>
<div class="Bd Bd-indent">C -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#RR_r8">RR r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="RRA"><a class="permalink" href="#RRA">RRA</a></h2>
Rotate register <b class="Sy">A</b> right through carry.
<p class="Pp"></p>
<div class="Bd Bd-indent">C -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: 0</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="RRC_r8"><a class="permalink" href="#RRC_r8">RRC r8</a></h2>
Rotate register <var class="Ar">r8</var> right.
<p class="Pp"></p>
<div class="Bd Bd-indent">[0] -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="RRC__HL_"><a class="permalink" href="#RRC__HL_">RRC
  [HL]</a></h2>
Rotate value pointed by <b class="Sy">HL</b> right.
<p class="Pp"></p>
<div class="Bd Bd-indent">[0] -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#RRC_r8">RRC r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="RRCA"><a class="permalink" href="#RRCA">RRCA</a></h2>
Rotate register <b class="Sy">A</b> right.
<p class="Pp"></p>
<div class="Bd Bd-indent">[0] -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: 0</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="RST_vec"><a class="permalink" href="#RST_vec">RST
  vec</a></h2>
Call restart vector <var class="Ar">vec</var>.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="SBC_A,r8"><a class="permalink" href="#SBC_A,r8">SBC
  A,r8</a></h2>
Subtract the value in <var class="Ar">r8</var> and the carry flag from
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 1</li>
  <li><b class="Sy">H</b>: Set if no borrow from bit 4.</li>
  <li><b class="Sy">C</b>: Set if no borrow (set if <var class="Ar">r8</var>
      &gt; <b class="Sy">A</b>).</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="SBC_A,_HL_"><a class="permalink" href="#SBC_A,_HL_">SBC
  A,[HL]</a></h2>
Subtract the value pointed by <b class="Sy">HL</b> and the carry flag from
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#SBC_A,r8">SBC A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="SBC_A,n8"><a class="permalink" href="#SBC_A,n8">SBC
  A,n8</a></h2>
Subtract the value <var class="Ar">n8</var> and the carry flag from
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#SBC_A,r8">SBC A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="SCF"><a class="permalink" href="#SCF">SCF</a></h2>
Set Carry Flag.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: 1</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="SET_u3,r8"><a class="permalink" href="#SET_u3,r8">SET
  u3,r8</a></h2>
Set bit <var class="Ar">u3</var> in register <var class="Ar">r8</var> to 1.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="SET_u3,_HL_"><a class="permalink" href="#SET_u3,_HL_">SET
  u3,[HL]</a></h2>
Set bit <var class="Ar">u3</var> in the byte pointed by <b class="Sy">HL</b> to
  1.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="SLA_r8"><a class="permalink" href="#SLA_r8">SLA r8</a></h2>
Shift left arithmetic register <var class="Ar">r8</var>.
<p class="Pp"></p>
<div class="Bd Bd-indent">C &lt;- [7 &lt;- 0] &lt;- 0</div>
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="SLA__HL_"><a class="permalink" href="#SLA__HL_">SLA
  [HL]</a></h2>
Shift left arithmetic value pointed by <b class="Sy">HL</b>.
<p class="Pp"></p>
<div class="Bd Bd-indent">C &lt;- [7 &lt;- 0] &lt;- 0</div>
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#SLA_r8">SLA r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="SRA_r8"><a class="permalink" href="#SRA_r8">SRA r8</a></h2>
Shift right arithmetic register <var class="Ar">r8</var>.
<p class="Pp"></p>
<div class="Bd Bd-indent">[7] -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="SRA__HL_"><a class="permalink" href="#SRA__HL_">SRA
  [HL]</a></h2>
Shift right arithmetic value pointed by <b class="Sy">HL</b>.
<p class="Pp"></p>
<div class="Bd Bd-indent">[7] -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#SRA_r8">SRA r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="SRL_r8"><a class="permalink" href="#SRL_r8">SRL r8</a></h2>
Shift right logic register <var class="Ar">r8</var>.
<p class="Pp"></p>
<div class="Bd Bd-indent">0 -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: Set according to result.</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="SRL__HL_"><a class="permalink" href="#SRL__HL_">SRL
  [HL]</a></h2>
Shift right logic value pointed by <b class="Sy">HL</b>.
<p class="Pp"></p>
<div class="Bd Bd-indent">0 -&gt; [7 -&gt; 0] -&gt; C</div>
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#SRA_r8">SRA r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="STOP"><a class="permalink" href="#STOP">STOP</a></h2>
Enter CPU very low power mode. Also used to switch between double and normal
  speed CPU modes in GBC.
<p class="Pp">Cycles: -</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: None affected.</p>
</section>
<section class="Ss">
<h2 class="Ss" id="SUB_A,r8"><a class="permalink" href="#SUB_A,r8">SUB
  A,r8</a></h2>
Subtract the value in <var class="Ar">r8</var> from <b class="Sy">A</b>.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 1</li>
  <li><b class="Sy">H</b>: Set if no borrow from bit 4.</li>
  <li><b class="Sy">C</b>: Set if no borrow (set if <var class="Ar">r8</var>
      &gt; <b class="Sy">A</b>).</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="SUB_A,_HL_"><a class="permalink" href="#SUB_A,_HL_">SUB
  A,[HL]</a></h2>
Subtract the value pointed by <b class="Sy">HL</b> from <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#SUB_A,r8">SUB A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="SUB_A,n8"><a class="permalink" href="#SUB_A,n8">SUB
  A,n8</a></h2>
Subtract the value <var class="Ar">n8</var> from <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#SUB_A,r8">SUB A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="SWAP_r8"><a class="permalink" href="#SWAP_r8">SWAP
  r8</a></h2>
Swap upper 4 bits in register <var class="Ar">r8</var> and the lower ones.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: 0</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="SWAP__HL_"><a class="permalink" href="#SWAP__HL_">SWAP
  [HL]</a></h2>
Swap upper 4 bits in the byte pointed by <b class="Sy">HL</b> and the lower
  ones.
<p class="Pp">Cycles: 4</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#SWAP_r8">SWAP r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="XOR_A,r8"><a class="permalink" href="#XOR_A,r8">XOR
  A,r8</a></h2>
Bitwise XOR between the value in <var class="Ar">r8</var> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 1</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags:</p>
<ul class="Bl-bullet Bl-compact">
  <li><b class="Sy">Z</b>: Set if result is 0.</li>
  <li><b class="Sy">N</b>: 0</li>
  <li><b class="Sy">H</b>: 0</li>
  <li><b class="Sy">C</b>: 0</li>
</ul>
</section>
<section class="Ss">
<h2 class="Ss" id="XOR_A,_HL_"><a class="permalink" href="#XOR_A,_HL_">XOR
  A,[HL]</a></h2>
Bitwise XOR between the value pointed by <b class="Sy">HL</b> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 1</p>
<p class="Pp">Flags: See <a class="Sx" href="#XOR_A,r8">XOR A,r8</a></p>
</section>
<section class="Ss">
<h2 class="Ss" id="XOR_A,n8"><a class="permalink" href="#XOR_A,n8">XOR
  A,n8</a></h2>
Bitwise XOR between the value in <var class="Ar">n8</var> and
  <b class="Sy">A</b>.
<p class="Pp">Cycles: 2</p>
<p class="Pp">Bytes: 2</p>
<p class="Pp">Flags: See <a class="Sx" href="#XOR_A,r8">XOR A,r8</a></p>
</section>
</section>
<section class="Sh">
<h1 class="Sh" id="SEE_ALSO"><a class="permalink" href="#SEE_ALSO">SEE
  ALSO</a></h1>
<a class="Xr">rgbasm(1)</a>, <a class="Xr">rgbds(7)</a>
</section>
<section class="Sh">
<h1 class="Sh" id="HISTORY"><a class="permalink" href="#HISTORY">HISTORY</a></h1>
<code class="Nm">rgbds</code> was originally written by Carsten S&#x00F8;rensen
  as part of the ASMotor package, and was later packaged in RGBDS by Justin
  Lloyd. It is now maintained by a number of contributors at
  <a class="Lk" href="https://github.com/rednex/rgbds">https://github.com/rednex/rgbds</a>.
</section>
</div>
<table class="foot">
  <tr>
    <td class="foot-date">February 23, 2018</td>
    <td class="foot-os">RGBDS Manual</td>
  </tr>
</table>
</body>
</html>