shithub: riscv

Download patch

ref: 0231537cbac846087f5ac132aba5c97ec9d4cffa
parent: 73ffc757d57e3b84fe62d679425be6be209fcfac
author: Ori Bernstein <ori@eigenstate.org>
date: Mon Dec 4 12:31:54 EST 2023 

ether8169: fix rx/tx on more recent realtek models (thanks uramekus)

Recent realtek models will not send packets if rx/tx is enabled before
configuration is complete. Additionally, the RXDV gate should be enabled
to put traffic on the fifo instead of the DMA controller.

this follows OpenBSD's sys/dev/pci/if_rge.c and FreeBSD's sys/dev/re/if_re.c


--- a/sys/src/9/pc/ether8169.c
+++ b/sys/src/9/pc/ether8169.c
@@ -125,7 +125,7 @@
 	Macv40		= 0x4c000000,	/* RTL8168G */
 	Macv42		= 0x50800000,	/* RTL8168GU */
 	Macv44		= 0x5c800000,	/* RTL8411B */
-	Macv45		= 0x54000000,	/* RTL8111HN */
+	Macv45		= 0x54000000,	/* RTL8111HN/8168H */
 	Macv51		= 0x50000000,	/* RTL8168EP */
 
 	Ifg0		= 0x01000000,	/* Interframe Gap 0 */
@@ -714,7 +714,9 @@
 	cplusc |= Txenb|Mulrw;
 	switch(ctlr->macv){
 	case Macv40:
+	case Macv42:
 	case Macv44:
+	case Macv45:
 	case Macv51:
 		cplusc |= Macstatdis;
 		break;
@@ -732,7 +734,20 @@
 	csr32w(ctlr, Rdsar+4, pa>>32);
 	csr32w(ctlr, Rdsar, pa);
 
-	csr8w(ctlr, Cr, Te|Re);
+	/* pre-RTL8168G controllers need TX/RX before configuration */
+	switch(ctlr->macv){
+	case Macv40:
+	case Macv42:
+	case Macv44:
+	case Macv45:
+	case Macv51:
+		/* RXDV gating */
+		i = csr32r(ctlr, 0x00F0);
+		csr32w(ctlr, 0x00F0, i&~0x00080000);
+		break;
+	default:
+		csr8w(ctlr, Cr, Te|Re);
+	}
 
 	csr32w(ctlr, Tcr, Ifg1|Ifg0|Mtxdmaunlimited);
 	ctlr->tcr = csr32r(ctlr, Tcr);
@@ -769,6 +784,16 @@
 
 	csr32w(ctlr, Mpc, 0);
 
+	switch(ctlr->macv){
+	case Macv40:
+	case Macv42:
+	case Macv44:
+	case Macv45:
+	case Macv51:
+		csr8w(ctlr, Cr, Te|Re);
+	default:
+		break;
+	}
 	iunlock(ctlr);
 }