ref: 2594b99629957d8ce380157e9af4a5feff86c5fe
parent: e6684dbfda0507565f44967680b850b35a5b4f93
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Sat Nov 21 11:26:46 EST 2020
pc, pc64: new MTRR code supporting AMD TOM2 MSR and fixed mtrr ranges The new MTRR code handles overlapping ranges and supports AMD specific TOM2 MSR. The format in /dev/archctl now only shows the effective cache ranges only, without exposing the low level registers.