shithub: riscv

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ref: 3bf49f18142a5d37bd5507d7491ba4eb223eb3b1
parent: ffd99348f3d1b474abd03183064caaa4209c11a6
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Fri Aug 16 15:05:04 EDT 2019 

bcm64: set XN bits for kernel device mappings


--- a/sys/src/9/bcm64/mem.h
+++ b/sys/src/9/bcm64/mem.h
@@ -54,6 +54,7 @@
 
 #define SPINTABLE	(KZERO+0xd8)
 #define CONFADDR	(KZERO+0x100)
+#define VECTORSEL2	(0x1000)
 #define	REBOOTADDR	(0x1c00)		/* reboot code - physical address */
 #define	VCBUFFER	(KZERO+0x3400)		/* videocore mailbox buffer */
 
@@ -114,6 +115,8 @@
 
 #define PTEAF		(1<<10)
 #define PTENG		(1<<11)
+#define PTEPXN		(1ULL<<53)
+#define PTEUXN		(1ULL<<54)
 
 #define PTEKERNEL	PTEAP(0)
 #define PTEUSER		PTEAP(1)
--- a/sys/src/9/bcm64/mmu.c
+++ b/sys/src/9/bcm64/mmu.c
@@ -11,7 +11,7 @@
 	uintptr va, pa, pe, attr;
 
 	/* KZERO */
-	attr = PTEWRITE | PTEAF | PTEKERNEL | PTESH(SHARE_INNER);
+	attr = PTEWRITE | PTEAF | PTEKERNEL | PTEUXN | PTESH(SHARE_INNER);
 	pe = PHYSDRAM + soc.dramsize;
 	if(pe > (uintptr)-KZERO)
 		pe = (uintptr)-KZERO;
@@ -34,7 +34,7 @@
 		l1[PTL1X(pa, 3)] = (uintptr)&l1[L1TABLEX(pa, 2)] | PTEVALID | PTETABLE;
 
 	/* VIRTIO */
-	attr = PTEWRITE | PTEAF | PTEKERNEL | PTESH(SHARE_OUTER) | PTEDEVICE;
+	attr = PTEWRITE | PTEAF | PTEKERNEL | PTEUXN | PTEPXN | PTESH(SHARE_OUTER) | PTEDEVICE;
 	pe = soc.physio + soc.iosize;
 	for(pa = soc.physio, va = soc.virtio; pa < pe; pa += PGLSZ(1), va += PGLSZ(1)){
 		if(((pa|va) & PGLSZ(1)-1) != 0){
@@ -49,7 +49,7 @@
 	}
 
 	/* ARMLOCAL */
-	attr = PTEWRITE | PTEAF | PTEKERNEL | PTESH(SHARE_OUTER) | PTEDEVICE;
+	attr = PTEWRITE | PTEAF | PTEKERNEL | PTEUXN | PTEPXN | PTESH(SHARE_OUTER) | PTEDEVICE;
 	pe = soc.armlocal + MB;
 	for(pa = soc.armlocal, va = ARMLOCAL; pa < pe; pa += PGLSZ(1), va += PGLSZ(1)){
 		if(((pa|va) & PGLSZ(1)-1) != 0){
@@ -65,7 +65,7 @@
 
 	/* VIRTPCI */
 	if(soc.pciwin){
-		attr = PTEWRITE | PTEAF | PTEKERNEL | PTESH(SHARE_OUTER) | PTEDEVICE;
+		attr = PTEWRITE | PTEAF | PTEKERNEL | PTEUXN | PTEPXN | PTESH(SHARE_OUTER) | PTEDEVICE;
 		pe = soc.pciwin + 512*MB;
 		for(pa = soc.pciwin, va = VIRTPCI; pa < pe; pa += PGLSZ(1), va += PGLSZ(1))
 			l1[PTL1X(va, 1)] = pa | PTEVALID | PTEBLOCK | attr;
@@ -185,9 +185,10 @@
 	off = pa % PGLSZ(1);
 	a = va + off;
 	pe = (pa + size + (PGLSZ(1)-1)) & -PGLSZ(1);
+	pa &= -PGLSZ(1);
 	while(pa < pe){
 		((uintptr*)L1)[PTL1X(va, 1)] = pa | PTEVALID | PTEBLOCK | PTEWRITE | PTEAF
-			| PTEKERNEL | PTESH(SHARE_OUTER) | attr;
+			| PTEKERNEL | PTEUXN | PTEPXN | PTESH(SHARE_OUTER) | attr;
 		pa += PGLSZ(1);
 		va += PGLSZ(1);
 	}
@@ -329,7 +330,7 @@
 		flushasidvall((uvlong)up->asid<<48 | va>>12);
 	else
 		flushasidva((uvlong)up->asid<<48 | va>>12);
-	*pte = pa | PTEPAGE | PTEUSER | PTENG | PTEAF | PTESH(SHARE_INNER);
+	*pte = pa | PTEPAGE | PTEUSER | PTEPXN | PTENG | PTEAF | PTESH(SHARE_INNER);
 	if(pg->txtflush & (1UL<<m->machno)){
 		/* pio() sets PG_TXTFLUSH whenever a text pg has been written */
 		cachedwbinvse((void*)KADDR(pg->pa), BY2PG);