shithub: riscv

Download patch

ref: 6c7d0aeb7d937a3dcf924f1ef2952ee6c7aa9eb3
parent: 511421003a44633d8907828aef280acc762cc56b
author: Jacob Moody <moody@posixcafe.org>
date: Sun May 19 17:53:53 EDT 2024 

ja: add RSP, RARG, and LR

These were used quite commonly in various assembly
files, just define it and declutter.


--- a/sys/src/ape/lib/9/riscv64/getcallerpc.s
+++ b/sys/src/ape/lib/9/riscv64/getcallerpc.s
@@ -1,5 +1,3 @@
-#define RARG	R8
-
 TEXT	getcallerpc(SB), 1, $0
 	MOV	0(SP), RARG
 	RET
--- a/sys/src/ape/lib/9/riscv64/getfcr.s
+++ b/sys/src/ape/lib/9/riscv64/getfcr.s
@@ -1,21 +1,19 @@
-#define ARG	8
-
 #define FFLAGS		1
 #define FRM		2
 #define FCSR		3
 
 TEXT	getfsr(SB), $0
-	MOV	CSR(FCSR), R(ARG)
+	MOV	CSR(FCSR), RARG
 	RET
 
 TEXT	setfsr(SB), $0
-	MOV	R(ARG), CSR(FCSR)
+	MOV	RARG, CSR(FCSR)
 	RET
 
 TEXT	getfcr(SB), $0
-	MOV	CSR(FCSR), R(ARG)
+	MOV	CSR(FCSR), RARG
 	RET
 
 TEXT	setfcr(SB), $0
-	MOV	R(ARG), CSR(FCSR)
+	MOV	RARG, CSR(FCSR)
 	RET
--- a/sys/src/ape/lib/ap/riscv64/cycles.s
+++ b/sys/src/ape/lib/ap/riscv64/cycles.s
@@ -1,5 +1,3 @@
-#define RARG R8
-
 /* user-accessible CSRs */
 #define CYCLO		0xc00
 
--- a/sys/src/ape/lib/ap/riscv64/getcallerpc.s
+++ b/sys/src/ape/lib/ap/riscv64/getcallerpc.s
@@ -1,5 +1,3 @@
-#define RARG	R8
-
 TEXT	getcallerpc(SB), 1, $0
 	MOV	0(SP), RARG
 	RET
--- a/sys/src/ape/lib/ap/riscv64/getfcr.s
+++ b/sys/src/ape/lib/ap/riscv64/getfcr.s
@@ -1,21 +1,19 @@
-#define ARG	8
-
 #define FFLAGS		1
 #define FRM		2
 #define FCSR		3
 
 TEXT	getfsr(SB), $0
-	MOV	CSR(FCSR), R(ARG)
+	MOV	CSR(FCSR), RARG
 	RET
 
 TEXT	setfsr(SB), $0
-	MOV	R(ARG), CSR(FCSR)
+	MOV	RARG, CSR(FCSR)
 	RET
 
 TEXT	getfcr(SB), $0
-	MOV	CSR(FCSR), R(ARG)
+	MOV	CSR(FCSR), RARG
 	RET
 
 TEXT	setfcr(SB), $0
-	MOV	R(ARG), CSR(FCSR)
+	MOV	RARG, CSR(FCSR)
 	RET
--- a/sys/src/cmd/gefs/atomic-riscv64.s
+++ b/sys/src/cmd/gefs/atomic-riscv64.s
@@ -22,7 +22,7 @@
 	FENCE_RW
 	AMOW(Amoswap, AQ|RL, 12, ARG, 10)
 	FENCE_RW
-	MOVW	R10, R(ARG)
+	MOVW	R10, RARG
 	RET
 
 TEXT asetv+0(SB),1,$0
@@ -31,7 +31,7 @@
 	FENCE_RW
 	AMOD(Amoswap, AQ|RL, 12, ARG, 10)
 	FENCE_RW
-	MOV	R10, R(ARG)
+	MOV	R10, RARG
 	RET
 
 /*  inc variants */
@@ -41,7 +41,7 @@
 	/* after: value before add in R10, value after add in memory */
 	AMOW(Amoadd, AQ|RL, 9, ARG, 10)
 	FENCE_RW
-	ADDW	$1, R10, R(ARG)		/* old value ±1 for ainc/adec */
+	ADDW	$1, R10, RARG		/* old value ±1 for ainc/adec */
 	RET
 
 TEXT aincv+0(SB),1,$0
@@ -51,7 +51,7 @@
 	/* after: value before add in R10, value after add in memory */
 	AMOD(Amoadd, AQ|RL, 9, ARG, 10)
 	FENCE_RW
-	ADDW	$1, R10, R(ARG)		/* old value ±1 for ainc/adec */
+	ADDW	$1, R10, RARG		/* old value ±1 for ainc/adec */
 	RET
 
 /*  cas variants */
@@ -61,18 +61,18 @@
 	MOV	R0, R11		/* default to failure */
 	FENCE_RW
 spincas:
-	LRW(ARG, 14)		/* (R(ARG)) -> R14 */
+	LRW(ARG, 14)		/* (RARG) -> R14 */
 	SLL	$32, R14
 	SRL	$32, R14	/* don't sign extend */
 	BNE	R12, R14, fail
 	FENCE_RW
-	SCW(13, ARG, 14)	/* R13 -> (R(ARG)) maybe, R14=0 if ok */
+	SCW(13, ARG, 14)	/* R13 -> (RARG) maybe, R14=0 if ok */
 	BNE	R14, spincas	/* R14 != 0 means store failed */
 ok:
 	MOV	$1, R11
 fail:
 	FENCE_RW
-	MOV	R11, R(ARG)
+	MOV	R11, RARG
 	RET
 
 TEXT acasv+0(SB),1,$0
@@ -82,10 +82,10 @@
 	MOV	R0, R11		/* default to failure */
 	FENCE_RW
 spincasp:
-	LRD(ARG, 14)		/* (R(ARG)) -> R14 */
+	LRD(ARG, 14)		/* (RARG) -> R14 */
 	BNE	R12, R14, fail
 	FENCE_RW
-	SCD(13, ARG, 14)	/* R13 -> (R(ARG)) maybe, R14=0 if ok */
+	SCD(13, ARG, 14)	/* R13 -> (RARG) maybe, R14=0 if ok */
 	BNE	R14, spincasp	/* R14 != 0 means store failed */
 	JMP	ok
 
--- a/sys/src/cmd/ja/lex.c
+++ b/sys/src/cmd/ja/lex.c
@@ -244,6 +244,10 @@
 	"F30",		LFREG,	30,
 	"F31",		LFREG,	31,
 
+	"RARG",		LREG,	REGARG,
+	"RSP",		LREG,	REGSP,
+	"LR",		LREG,	1,
+
 	"CSR",		LCTL,	0,
 
 	"ADD",		LADD,	AADD,
--- a/sys/src/libc/riscv64/cycles.s
+++ b/sys/src/libc/riscv64/cycles.s
@@ -1,5 +1,3 @@
-#define RARG R8
-
 /* user-accessible CSRs */
 #define CYCLO		0xc00
 
--- a/sys/src/libc/riscv64/getcallerpc.s
+++ b/sys/src/libc/riscv64/getcallerpc.s
@@ -1,5 +1,3 @@
-#define RARG	R8
-
 TEXT	getcallerpc(SB), 1, $0
 	MOV	0(SP), RARG
 	RET
--- a/sys/src/libc/riscv64/getfcr.s
+++ b/sys/src/libc/riscv64/getfcr.s
@@ -1,5 +1,3 @@
-#define ARG	8
-
 #define FFLAGS		1
 #define FRM		2
 #define FCSR		3
@@ -6,10 +4,10 @@
 
 TEXT	getfcr(SB), $-4
 TEXT	getfsr(SB), $-4
-	MOV	CSR(FCSR), R(ARG)
+	MOV	CSR(FCSR), RARG
 	RET
 
 TEXT	setfcr(SB), $-4
 TEXT	setfsr(SB), $-4
-	MOV	R(ARG), CSR(FCSR)
+	MOV	RARG, CSR(FCSR)
 	RET
--- a/sys/src/libc/riscv64/setjmp.s
+++ b/sys/src/libc/riscv64/setjmp.s
@@ -1,9 +1,6 @@
-#define LINK	R1
-#define RARG	R8
-
 TEXT	setjmp(SB), 1, $-4
 	MOV	R2, (RARG)	/* store sp in jmp_buf */
-	MOV	LINK, XLEN(RARG) /* store return pc */
+	MOV	LR, XLEN(RARG) /* store return pc */
 	MOV	R0, RARG	/* return 0 */
 	RET
 
@@ -12,6 +9,6 @@
 	BNE	R13, ok		/* ansi: "longjmp(0) => longjmp(1)" */
 	MOV	$1, R13		/* bless their pointed heads */
 ok:	MOV	(RARG), R2	/* restore sp */
-	MOV	XLEN(RARG), LINK /* restore return pc */
+	MOV	XLEN(RARG), LR /* restore return pc */
 	MOV	R13, RARG
 	RET			/* jump to saved pc */