shithub: riscv

Info  •  Files  •  Log  •  Branches

6l: no need to emit rex.w prefix for MOVBQZX and MOVWQZX

as with 32 bit operand size, the upper bits 63:32 are
automatically zeroed in 64bit mode. this gives a shoter
instruction encoding.

--- a/sys/src/cmd/6l/optab.c

+++ b/sys/src/cmd/6l/optab.c

@@ -751,7 +751,7 @@

 	{ AMOVBLSX,	ymb_rl,	Pm, 0xbe },

 	{ AMOVBLZX,	ymb_rl,	Pm, 0xb6 },

 	{ AMOVBQSX,	ymb_rl,	Pw, 0x0f,0xbe },

-	{ AMOVBQZX,	ymb_rl,	Pw, 0x0f,0xb6 },

+	{ AMOVBQZX,	ymb_rl,	Py, 0x0f,0xb6 },

 	{ AMOVBWSX,	ymb_rl,	Pq, 0xbe },

 	{ AMOVBWZX,	ymb_rl,	Pq, 0xb6 },

 	{ AMOVO,	yxmov,	Pe, 0x6f,0x7f },

@@ -786,7 +786,7 @@

 	{ AMOVWLSX,	yml_rl,	Pm, 0xbf },

 	{ AMOVWLZX,	yml_rl,	Pm, 0xb7 },

 	{ AMOVWQSX,	yml_rl,	Pw, 0x0f,0xbf },

-	{ AMOVWQZX,	yml_rl,	Pw, 0x0f,0xb7 },

+	{ AMOVWQZX,	yml_rl,	Py, 0x0f,0xb7 },

 	{ AMULB,	ydivb,	Pb, 0xf6,(04) },

 	{ AMULL,	ydivl,	Px, 0xf7,(04) },

 	{ AMULPD,	yxm,	Pe, 0x59 },

-- 

⑨