shithub: riscv

Download patch

ref: 8aaecfe55f73a8c599fed1adbbba11a5e94dfc3c
parent: 47165e1c2ccc0471349691cc92f64f81984b18c5
author: Sigrid Solveig Haflínudóttir <sigrid@ftrv.se>
date: Tue May 9 10:24:23 EDT 2023

7l: throw an error if CASE uses the same register for base and offset (CASE R1, R1)

--- a/sys/src/cmd/7l/asmout.c
+++ b/sys/src/cmd/7l/asmout.c
@@ -818,6 +818,8 @@
 		break;
 
 	case 62:	/* case Rv, Rt -> adr tab, Rt; movw Rt[R<<2], Rl; add Rt, Rl; br (Rl) */
+		if(p->from.reg == p->to.reg)
+			diag("invalid SWITCH\n%P", p);
 		o1 = ADR(0, 4*4, p->to.reg);	/* adr 4(pc), Rt */
 		o2 = (2<<30)|(7<<27)|(2<<22)|(1<<21)|(3<<13)|(1<<12)|(2<<10)|(p->from.reg<<16)|(p->to.reg<<5)|REGTMP;	/* movw Rt[Rv<<2], REGTMP */
 		o3 = oprrr(AADD) | (p->to.reg<<16) | (REGTMP<<5) | REGTMP;	/* add Rt, REGTMP */