ref: a3b95d3e567c0ef60f9f1ead26124fb706dec20d
parent: 0bc0f1cfcec73baddc58cab9a61c720bb8c15077
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Sun Jun 11 09:09:44 EDT 2023
7c: implement bit rotations using ROR/EXT instruction
--- a/sys/src/cmd/7c/cgen.c
+++ b/sys/src/cmd/7c/cgen.c
@@ -199,6 +199,7 @@
case OADD:
case OAND:
case OOR:
+ case OROL:
case OLSHR:
case OASHL:
case OASHR:
--- a/sys/src/cmd/7c/peep.c
+++ b/sys/src/cmd/7c/peep.c
@@ -481,6 +481,7 @@
case ALSL:
case ALSR:
case AASR:
+ case AROR:
case AORR:
case AAND:
case AANDS:
@@ -502,6 +503,7 @@
case ALSLW:
case ALSRW:
case AASRW:
+ case ARORW:
case AORRW:
case AANDW:
case AANDSW:
@@ -1173,6 +1175,8 @@
case ALSRW:
case AASR:
case AASRW:
+ case AROR:
+ case ARORW:
case AORR:
case AORRW:
case AAND:
@@ -1331,6 +1335,8 @@
case ALSRW:
case AASR:
case AASRW:
+ case AROR:
+ case ARORW:
case AORR:
case AORRW:
case AAND:
--- a/sys/src/cmd/7c/sgen.c
+++ b/sys/src/cmd/7c/sgen.c
@@ -181,6 +181,18 @@
simplifyshift(n);
break;
+ case OOR:
+ xcom(l);
+ xcom(r);
+ switch(n->type->etype){+ case TUINT:
+ case TULONG:
+ case TUVLONG:
+ rolor(n);
+ break;
+ }
+ break;
+
default:
if(l != Z)
xcom(l);
--- a/sys/src/cmd/7c/txt.c
+++ b/sys/src/cmd/7c/txt.c
@@ -1037,6 +1037,16 @@
a = AORR;
break;
+ case OROL:
+ if(isv(et)){+ a = AROR;
+ f1->vconst = 64-f1->vconst;
+ } else {+ a = ARORW;
+ f1->vconst = 32-f1->vconst;
+ }
+ break;
+
case OASAND:
case OAND:
a = AANDW;
--- a/sys/src/libmach/7db.c
+++ b/sys/src/libmach/7db.c
@@ -159,6 +159,7 @@
"1001001101000000011111nnnnnddddd", "SXTW", "R%n,R%d",
"0101001100iiiiii011111nnnnnddddd", "LSRW", "$%i,R%n,R%d",
"1101001101iiiiii111111nnnnnddddd", "LSR", "$%i,R%n,R%d",
+ "W00100111-0mmmmmiiiiiinnnnnddddd", "EXTR%W", "$%i,R%m,R%n,R%d",
"W00100110-iiiiiijjjjjjnnnnnddddd", "SBFM%W", "$%i,$%j,R%n,R%d",
"W01100110-iiiiiijjjjjjnnnnnddddd", "BFM%W", "$%i,$%j,R%n,R%d",
"W10100110-iiiiiijjjjjjnnnnnddddd", "UBFM%W", "$%i,$%j,R%n,R%d",