ref: d069c9b486d2a2b9b26294023dd397f366d5e5ba
parent: 4e00cf6b1798fc95b3ccad8cb66a3e80c96b2786
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Sat Nov 15 10:21:24 EST 2014
pc: get rid of fixed 8MB memory map (now dynamically between 4 to 16 MB depending on kernel size) we now do mapping of KZERO to ROUND(end, 4*MB) where end needs not to be above 16MB. this allows for bigger kernels.
--- a/sys/src/9/pc/l.s
+++ b/sys/src/9/pc/l.s
@@ -162,46 +162,45 @@
TEXT mode32bit(SB), $0
/* At this point, the GDT setup is done. */
- MOVL $PADDR(CPU0PDB), DI /* clear 4 pages for the tables etc. */
+ MOVL $((CPU0END-CPU0PDB)>>2), CX
+ MOVL $PADDR(CPU0PDB), DI
XORL AX, AX
- MOVL $(4*BY2PG), CX
- SHRL $2, CX
CLD
REP; STOSL
+ MOVL $PADDR(CPU0PTE), DX
+ MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
+ ORL BX, DX
+
MOVL $PADDR(CPU0PDB), AX
ADDL $PDO(KZERO), AX /* page directory offset for KZERO */
- MOVL $PADDR(CPU0PTE), (AX) /* PTE's for KZERO */
- MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
- ORL BX, (AX)
- ADDL $4, AX
- MOVL $PADDR(CPU0PTE1), (AX) /* PTE's for KZERO+4MB */
- MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
- ORL BX, (AX)
+ MOVL DX, 0(AX) /* PTE's for KZERO */
+ ADDL $BY2PG, DX
+ MOVL DX, 4(AX) /* PTE's for KZERO+4MB */
+ ADDL $BY2PG, DX
+ MOVL DX, 8(AX) /* PTE's for KZERO+8MB */
+ ADDL $BY2PG, DX
+ MOVL DX, 12(AX) /* PTE's for KZERO+12MB */
MOVL $PADDR(CPU0PTE), AX /* first page of page table */
- MOVL $1024, CX /* 1024 pages in 4MB */
+ MOVL $end-KZERO(SB), CX
+ ADDL $(BY2XPG-1), CX
+ ANDL $~(BY2XPG-1), CX /* round to 4MB */
+ MOVL CX, MemMin-KZERO(SB) /* see memory.c */
+ SHRL $PGSHIFT, CX
+ MOVL BX, DX
_setpte:
- MOVL BX, (AX)
- ADDL $(1<<PGSHIFT), BX
+ MOVL DX, (AX)
+ ADDL $BY2PG, DX
ADDL $4, AX
LOOP _setpte
- MOVL $PADDR(CPU0PTE1), AX /* second page of page table */
- MOVL $1024, CX /* 1024 pages in 4MB */
-_setpte1:
- MOVL BX, (AX)
- ADDL $(1<<PGSHIFT), BX
- ADDL $4, AX
- LOOP _setpte1
-
MOVL $PADDR(CPU0PTE), AX
ADDL $PTO(MACHADDR), AX /* page table entry offset for MACHADDR */
- MOVL $PADDR(CPU0MACH), (AX) /* PTE for Mach */
- MOVL $(PTEWRITE|PTEVALID), BX /* page permissions */
- ORL BX, (AX)
+ ORL $PADDR(CPU0MACH), BX
+ MOVL BX, (AX) /* PTE for Mach */
/*
* Now ready to use the new map. Make sure the processor options are what is wanted.
--- a/sys/src/9/pc/mem.h
+++ b/sys/src/9/pc/mem.h
@@ -63,12 +63,14 @@
#define REBOOTADDR (0x11000) /* reboot code - physical address */
#define CPU0PDB (KZERO+0x12000) /* bootstrap processor PDB */
#define CPU0PTE (KZERO+0x13000) /* bootstrap processor PTE's for 0-4MB */
-#define CPU0GDT (KZERO+0x14000) /* bootstrap processor GDT */
-#define MACHADDR (KZERO+0x15000) /* as seen by current processor */
-#define CPU0MACH (KZERO+0x16000) /* Mach for bootstrap processor */
+#define CPU0PTE1 (KZERO+0x14000) /* bootstrap processor PTE's for 4-8MB */
+#define CPU0PTE2 (KZERO+0x15000) /* bootstrap processor PTE's for 8-12MB */
+#define CPU0PTE3 (KZERO+0x16000) /* bootstrap processor PTE's for 12-16MB */
+#define CPU0GDT (KZERO+0x17000) /* bootstrap processor GDT */
+#define MACHADDR (KZERO+0x18000) /* as seen by current processor */
+#define CPU0MACH (KZERO+0x19000) /* Mach for bootstrap processor */
#define MACHSIZE BY2PG
-#define CPU0PTE1 (KZERO+0x17000) /* bootstrap processor PTE's for 4MB-8MB */
-#define CPU0END (CPU0PTE1+BY2PG)
+#define CPU0END (CPU0MACH+BY2PG)
/*
* N.B. ramscan knows that CPU0END is the end of reserved data
* N.B. _startPADDR knows that CPU0PDB is the first reserved page
--- a/sys/src/9/pc/memory.c
+++ b/sys/src/9/pc/memory.c
@@ -15,6 +15,8 @@
#define MEMDEBUG 0
+u32int MemMin = 8*MB; /* set in l.s */
+
enum {MemUPA = 0, /* unbacked physical address */
MemRAM = 1, /* physical memory */
@@ -24,7 +26,6 @@
KB = 1024,
- MemMin = 8*MB,
MemMax = (3*1024+768)*MB,
};