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imx8: make gpc functionality available with a powerup() function

--- a/sys/src/9/imx8/fns.h

+++ b/sys/src/9/imx8/fns.h

@@ -145,5 +145,8 @@

 extern void setclkrate(char *name, char *source, int freq);

 extern int getclkrate(char *name);

+/* gpc */

+extern void powerup(char *dom);

+

 /* lcd */

 extern void lcdinit(void);

--- /dev/null

+++ b/sys/src/9/imx8/gpc.c

@@ -1,0 +1,63 @@

+#include "u.h"

+#include "../port/lib.h"

+#include "mem.h"

+#include "dat.h"

+#include "fns.h"

+#include "io.h"

+

+/* power gating controller registers */

+enum {

+	GPC_PGC_CPU_0_1_MAPPING	= 0xEC/4,

+	GPC_PGC_PU_PGC_SW_PUP_REQ = 0xF8/4,

+	GPC_PGC_PU_PGC_SW_PDN_REQ = 0x104/4,

+};

+

+static u32int *gpc = (u32int*)(VIRTIO + 0x3A0000);

+

+typedef struct Tab Tab;

+struct Tab {

+	char	*dom;

+	uint	mask;

+};

+

+static Tab pu_tab[] = {

+	"mipi",		1<<0,

+	"pcie",		1<<1,

+	"usb_otg1",	1<<2,

+	"usb_otg2",	1<<3,

+	"ddr1",		1<<5,

+	"ddr2",		1<<6,

+	"gpu",		1<<7,

+	"vpu",		1<<8,

+	"hdmi",		1<<9,

+	"disp",		1<<10,

+	"mipi_csi1",	1<<11,

+	"mipi_csi2",	1<<12,

+	"pcie2",	1<<13,

+

+	nil,

+};

+

+void

+powerup(char *dom)

+{

+	Tab *t;

+

+	if(dom == nil)

+		return;

+

+	for(t = pu_tab; t->dom != nil; t++)

+		if(cistrcmp(dom, t->dom) == 0)

+			goto Found;

+

+	panic("powerup: domain %s not defined", dom);

+

+Found:

+	gpc[GPC_PGC_CPU_0_1_MAPPING] = 0x0000FFFF;

+

+	gpc[GPC_PGC_PU_PGC_SW_PUP_REQ] |= t->mask;

+	while(gpc[GPC_PGC_PU_PGC_SW_PUP_REQ] & t->mask)

+		;

+

+	gpc[GPC_PGC_CPU_0_1_MAPPING] = 0;

+}

--- a/sys/src/9/imx8/lcd.c

+++ b/sys/src/9/imx8/lcd.c

@@ -39,19 +39,6 @@

 	GPIO_EDGE_SEL = 0x1C/4,

 };

-/* power gating controller registers */

-enum {

-	GPC_PGC_CPU_0_1_MAPPING	= 0xEC/4,

-	GPC_PGC_PU_PGC_SW_PUP_REQ = 0xF8/4,

-

-	GPC_A53_PU_PGC_PUP_STATUS0 = 0x1C4/4,

-	GPC_A53_PU_PGC_PUP_STATUS1 = 0x1C8/4,

-	GPC_A53_PU_PGC_PUP_STATUS2 = 0x1CC/4,

-		DISP_SW_PUP_REQ	= 1<<10,

-		HDMI_SW_PUP_REQ	= 1<<9,

-		MIPI_SW_PUP_REQ = 1<<0,

-};

-

 /* system reset controller registers */

 enum {

 	SRC_MIPIPHY_RCR = 0x28/4,

@@ -393,7 +380,6 @@

 static u32int *pwm2 = (u32int*)(VIRTIO + 0x670000);

 static u32int *resetc= (u32int*)(VIRTIO + 0x390000);

-static u32int *gpc =   (u32int*)(VIRTIO + 0x3A0000);

 static u32int *dsi =   (u32int*)(VIRTIO + 0xA00000);

 static u32int *dphy =  (u32int*)(VIRTIO + 0xA00300);

@@ -875,11 +861,7 @@

 	bridge->subaddr = 1;

 	/* power on mipi dsi */

-	wr(gpc, GPC_PGC_CPU_0_1_MAPPING, 0x0000FFFF);

-	mr(gpc, GPC_PGC_PU_PGC_SW_PUP_REQ, MIPI_SW_PUP_REQ, MIPI_SW_PUP_REQ);

-	while(rr(gpc, GPC_PGC_PU_PGC_SW_PUP_REQ) & MIPI_SW_PUP_REQ)

-		;

-	wr(gpc, GPC_PGC_CPU_0_1_MAPPING, 0);

+	powerup("mipi");

 	mr(resetc, SRC_MIPIPHY_RCR, 0, RCR_MIPI_DSI_RESET_N);

 	mr(resetc, SRC_MIPIPHY_RCR, 0, RCR_MIPI_DSI_PCLK_RESET_N);

--- a/sys/src/9/imx8/reform

+++ b/sys/src/9/imx8/reform

@@ -36,6 +36,7 @@

 	ipmux

 misc

 	ccm

+	gpc

 	gic

 	uartimx

 	lcd

--- a/sys/src/9/imx8/usbxhciimx.c

+++ b/sys/src/9/imx8/usbxhciimx.c

@@ -1809,26 +1809,6 @@

 }

 static void

-powerup(int i)

-{

-	/* power gating controller registers */

-	enum {

-		GPC_PGC_CPU_0_1_MAPPING	= 0xEC/4,

-		GPC_PGC_PU_PGC_SW_PUP_REQ = 0xF8/4,

-			USB_OTG1_SW_PUP_REQ = 1<<2,

-	};

-	static u32int *gpc = (u32int*)(VIRTIO + 0x3A0000);

-

-	gpc[GPC_PGC_CPU_0_1_MAPPING] = 0x0000FFFF;

-

-	gpc[GPC_PGC_PU_PGC_SW_PUP_REQ] |= (USB_OTG1_SW_PUP_REQ<<i);

-	while(gpc[GPC_PGC_PU_PGC_SW_PUP_REQ] & (USB_OTG1_SW_PUP_REQ<<i))

-		;

-

-	gpc[GPC_PGC_CPU_0_1_MAPPING] = 0;

-}

-

-static void

 phyinit(u32int *reg)

 {

 	enum {

@@ -1874,6 +1854,7 @@

 static int

 reset(Hci *hp)

 {

+	static char *powerdom[] = { "usb_otg1", "usb_otg2" };

 	static Ctlr ctlrs[2];

 	Ctlr *ctlr;

 	int i;

@@ -1915,7 +1896,7 @@

 		setclkrate("ccm_usb_phy_ref_clk_root", "system_pll1_div8", 100*Mhz);

 		i = 0;

 	}

-	powerup(i);

+	powerup(powerdom[i]);

 	clkenable(i, 1);

 	phyinit(&ctlr->mmio[0xF0040/4]);

 	coreinit(ctlr->mmio);