shithub: riscv

Download patch

ref: e2ddc61fed70c120ed61540181d1212f2cb05567
parent: ddbe5dd29a90b5750b816105a830a420baaea269
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Sun Nov 12 12:13:40 EST 2023

zynq: remove uartconsole() function, already done by devuart internally

--- a/sys/src/9/zynq/fns.h
+++ b/sys/src/9/zynq/fns.h
@@ -24,7 +24,7 @@
 #define VA(k) ((void*)(k))
 #define PTR2UINT(p) ((uintptr)(p))
 
-void uartinit(void);
+void uartconsinit(void);
 void mmuinit(void);
 uintptr ttbget(void);
 void ttbput(uintptr);
@@ -50,7 +50,6 @@
 void intrenable(int, void (*)(Ureg *, void *), void *, int, char *);
 void intrinit(void);
 int intr(Ureg *);
-int uartconsole(void);
 long fbctlread(Chan*,void*,long,vlong);
 long fbctlwrite(Chan*,void*,long,vlong);
 void fpoff(void);
--- a/sys/src/9/zynq/main.c
+++ b/sys/src/9/zynq/main.c
@@ -206,7 +206,6 @@
 	int i;
 
 	chandevinit();
-	uartconsole();
 	
 	if(!waserror()){
 		ksetenv("cputype", "arm", 0);
@@ -321,7 +320,7 @@
 		schedinit();
 		return;
 	}
-	uartinit();
+	uartconsinit();
 	mmuinit();
 	l2init();
 	intrinit();
--- a/sys/src/9/zynq/uartzynq.c
+++ b/sys/src/9/zynq/uartzynq.c
@@ -30,8 +30,6 @@
 	int irq, iena;
 } Ctlr;
 
-Uart* uartenable(Uart *);
-
 extern PhysUart zynqphysuart;
 
 static Ctlr zctlr[1] = {
@@ -53,9 +51,11 @@
 };
 
 void
-uartinit(void)
+uartconsinit(void)
 {
 	consuart = zuart;
+	uartctl(consuart, "l8 pn s1");
+	uartputs(kmesg.buf, kmesg.n);
 }
 
 static Uart *
@@ -145,22 +145,6 @@
 		;
 	ct->r[FIFO] = c;
 	return;
-}
-
-int
-uartconsole(void)
-{
-	Uart *uart = zuart;
-
-	if(up == nil)
-		return -1;
-
-	if(uartenable(uart) != nil){
-		serialoq = uart->oq;
-		uart->opens++;
-		consuart = uart;
-	}
-	return 0;
 }
 
 int