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ref: f17a5cc2cf345921f9036e23dfd895a9ee68a0e5
parent: 2ee4c089741823aae794eaa2eb53780f65019981
author: cinap_lenrek <cinap_lenrek@felloff.net>
date: Sun Oct 28 02:05:43 EDT 2018

bcm: fix l2 cache maintenance routines for raspi3 (armv8)

armv8 has 16-way l2, so adjust shift for the set-way cache
tag format.

--- a/sys/src/9/bcm/cache.v7.s
+++ b/sys/src/9/bcm/cache.v7.s
@@ -132,17 +132,6 @@
 	MOVW.P	8(R13), R15
 
 /*
- * these shift values are for the Cortex-A8 L1 cache (A=2, L=6) and
- * the Cortex-A8 L2 cache (A=3, L=6).
- * A = log2(# of ways), L = log2(bytes per cache line).
- * see armv7 arch ref p. 1403.
- */
-#define L1WAYSH 30
-#define L1SETSH 6
-#define L2WAYSH 29
-#define L2SETSH 6
-
-/*
  * callers are assumed to be the above l1 and l2 ops.
  * R0 is the function to call in the innermost loop.
  * R8 is the cache level (one-origin: 1 or 2).
@@ -184,11 +173,12 @@
 	ADD	$1, R2		/* R2 (sets) = ((R0 >> 13) & MASK(15)) + 1 */
 
 	/* precompute set/way shifts for inner loop */
+	MOVW	$6, R4
 	CMP	$0, R8		/* cache == 1? */
-	MOVW.EQ	$L1WAYSH, R3 	/* yes */
-	MOVW.EQ	$L1SETSH, R4
-	MOVW.NE	$L2WAYSH, R3	/* no */
-	MOVW.NE	$L2SETSH, R4
+	MOVW.EQ	$30, R3 	/* l1 */
+	MOVW.NE	$29, R3		/* l2 */
+	CMP	$16, R5		/* armv8 has 16-way l2, adjust shift */
+	MOVW.EQ	$28, R3
 
 	/* iterate over ways */
 	MOVW	$0, R7		/* R7: way */