ref: f1dca0e4408e6fcf85a11835e21875d035f783dd
parent: 4f56a35f2325cdea1665330545fe2befd1e0577e
author: Paul Brossier <piem@piem.org>
date: Sat Nov 3 12:51:26 EDT 2007
fvec test: change order in assertEqual
--- a/tests/python/fvec.py
+++ b/tests/python/fvec.py
@@ -21,7 +21,7 @@
""" check new fvec elements are set to 0. """
for index in range(buf_size):
for channel in range(channels):
- self.assertEqual(fvec_read_sample(self.vector,channel,index),0.)
+ self.assertEqual(0., fvec_read_sample(self.vector,channel,index))
def test_fvec_write_sample(self):
""" check new fvec elements are set with fvec_write_sample """
@@ -30,7 +30,7 @@
fvec_write_sample(self.vector,1.,channel,index)
for index in range(buf_size):
for channel in range(channels):
- self.assertEqual(fvec_read_sample(self.vector,channel,index),1.)
+ self.assertEqual(1., fvec_read_sample(self.vector,channel,index))
if __name__ == '__main__':
unittest.main()