shithub: lwext4

ref: 273f02b2eb705250f7e53ead6ab41237a0085713
dir: /demos/stm32f429_disco/pll.c/

/**
 * @file 	pll.c
 * @version 0.01
 * @date 	Oct 2, 2012
 * @author 	Grzegorz Kostka, kostka.grzegorz@gmail.com
 * @brief	...
 *
 * @note
 *
 * @addtogroup group
 * @{
 *		@addtogroup subgroup
 *		@{
 **********************************************************/
#include <config.h>
#include <pll.h>

#include <stm32f4xx.h>


#define PLL_FREQUENCY	CFG_CCLK_FREQ
#define PLL_CRYSTAL		8000000UL

static void flash_latency(uint32_t frequency)
{
	uint32_t wait_states;

	wait_states = frequency / 30000000ul;	// calculate wait_states (30M is valid for 2.7V to 3.6V voltage range, use 24M for 2.4V to 2.7V, 18M for 2.1V to 2.4V or 16M for  1.8V to 2.1V)
	wait_states &= 7;						// trim to max allowed value - 7

	FLASH->ACR = wait_states;				// set wait_states, disable all caches and prefetch
	FLASH->ACR = FLASH_ACR_DCRST | FLASH_ACR_ICRST | wait_states;	// reset caches
	FLASH->ACR = FLASH_ACR_DCEN | FLASH_ACR_ICEN | FLASH_ACR_PRFTEN | wait_states;	// enable caches and prefetch
}

static void fpu_enable(void)
{
#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
	SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2));	// set CP10 and CP11 Full Access
#endif
}

void pll_init(void)
{
	uint32_t div, mul, div_core, vco_input_frequency, vco_output_frequency, frequency_core;
	uint32_t best_div = 0, best_mul = 0, best_div_core = 0, best_frequency_core = 0;

	fpu_enable();
	RCC->CR |= ((uint32_t)RCC_CR_HSEON);	// enable HSE clock
	flash_latency(PLL_FREQUENCY);				// configure Flash latency for desired frequency

	for (div = 2; div <= 63; div++)			// PLLM in [2; 63]
	{
		vco_input_frequency = PLL_CRYSTAL / div;

		if ((vco_input_frequency < 1000000ul) || (vco_input_frequency > 2000000))	// skip invalid settings
			continue;

		for (mul = 64; mul <= 432; mul++)	// PLLN in [64; 432]
		{
			vco_output_frequency = vco_input_frequency * mul;

			if ((vco_output_frequency < 64000000ul) || (vco_output_frequency > 432000000ul))	// skip invalid settings
				continue;

			for (div_core = 2; div_core <= 8; div_core += 2)	// PLLP in {2, 4, 6, 8}
			{
				frequency_core = vco_output_frequency / div_core;

				if (frequency_core > CFG_CCLK_FREQ)	// skip values over desired frequency
					continue;

				if (frequency_core > best_frequency_core)	// is this configuration better than previous one?
				{
					best_frequency_core = frequency_core;	// yes - save values
					best_div = div;
					best_mul = mul;
					best_div_core = div_core;
				}
			}
		}
	}

	/* Configure PLL factors, always divide USB clock by 9 */
	RCC->PLLCFGR = (best_div << 0) 					|
				   (best_mul << 6) 					|
				   ((best_div_core / 2 - 1) << 16) 	|
				   (9 << 24) 						|
				   RCC_PLLCFGR_PLLSRC_HSE;

	/* AHB - no prescaler, APB1 - divide by 4, APB2 - divide by 2 */
	RCC->CFGR = RCC_CFGR_PPRE2_DIV2 |
				RCC_CFGR_PPRE1_DIV4 |
				RCC_CFGR_HPRE_DIV1;


	/* Wait for stable clock */
	while (!(RCC->CR & RCC_CR_HSERDY))
		;

    /* Enable the main PLL */
    RCC->CR |= RCC_CR_PLLON;

    /* Wait for PLL lock */
	while (!(RCC->CR & RCC_CR_PLLRDY))
		;

	/* Change SYSCLK to PLL */
	RCC->CFGR |= RCC_CFGR_SW_PLL;

	/* Wait for switch */
	while (((RCC->CFGR) & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
		;
}


/** 	@} (end addtogroup subgroup) 	*/
/** @} (end addtogroup group) 			*/